The present invention relates to an information processing apparatus for executing a data transfer instruction to store data or information stored at one address of a memory to another address of the same memory.
A transfer instruction usually includes a source address, a destination address and a designation of the lengths of the operands to be transferred. The source address is the address of the source, and the destination address, that of the destination, in said memory.
Some transfer instructions require the transfer of operand data byte by byte from the source operand data region (hereinafter called source operands) to the destination operand data region (hereinafter called destination operands).
Generally, data reading out of or writing into a main storage or a cache memory in an information processing apparatus takes place word by word, each word having a fixed length of four bytes or eight bytes. Therefore, other transfer instructions requires the transfer of data, instead of byte by byte, in four-byte or eight-byte words. This word-by-word data transfer realizes improved performance in the execution of transfer instructions than a byte-by-byte data transfer. Where the source operands include a destination address in a word-by-word data transfer, there arises the problem of difference in results between byte-by-byte and word-by-word transfers.
If address regions overlap one another in such data transfer, the execution of the transfer instruction should be so altered as to transfer the data byte by byte, instead of word by word.
For one example of a technique to improve the performance of executing a transfer instruction where such an overlap is present, reference may be made to the U.S. Pat. No. 4,652,991.
Irrespective of improving the performance in an overlapping situation, however, there is the need to detect any destructive overlapping of operands. The aforementioned U.S. Pat. No 4,652,991 also describes an example of such detecting technique.
Usually, this detection uses the source address, destination address and source operand length to check whether or not the following condition holds:
______________________________________ source address .ltoreq. destination address &lt; (source address + source operand length) ______________________________________
This detecting system, however, first of all requires for the detection of any destructive overlap the equal availability of the source address, destination address and source operand length.
It further requires the arithmetic operation of adding the source address and the source operand length, comparison of the relative magnitudes of elements in two combinations, one between the source address and the destination address and the other between the destination address and the source address plus the source operand length, arithmetic operation of subtracting the source address from the destination address, and comparison of the relative magnitudes between the balance of the subtraction of the source address from the destination address and the source operand length.
Therefore, the detection of any destructive overlap would take a considerable length of time. Moreover, even if there is no destructive overlap, the data transfer is started after the absence of destructive overlap is detected, so that it is difficult to improve the performance of executing transfer instructions even though data are transferred word by word.
An object of the present invention is to provide an information transfer apparatus cleared of the abovementioned disadvantage and capable of improving the performance of executing transfer instructions.